The present invention relates generally to electronic displays and methods of manufacturing the electronic displays, and more particularly to, semiconductor devices for electronic display applications and methods of manufacturing the semiconductor devices.
Some encapsulated, particle-based displays offer a useful means of creating electronic displays. There exist many versions of encapsulated particle-based displays including encapsulated electrophoretic displays, encapsulated suspended particle displays, and rotating ball displays.
Encapsulated, particle-based displays can be made highly reflective, bistable, and optically and electrically efficient. To obtain a high-resolution display, however, individual pixels of a display must be addressable without interference from adjacent pixels. One way to achieve this objective is to provide an array of nonlinear elements, such as transistors or diodes where each transistor or diode is associated with each pixel. An addressing electrode is connected to each pixel through the transistor or the diode.
The processes for manufacturing active matrix arrays of thin-film transistors and diodes are well established in the display technology. Thin-film transistors, for example, can be fabricated using various deposition and photolithography techniques. A transistor includes a gate electrode, an insulating dielectric layer, a semiconductor layer and source and drain electrodes. Application of a voltage to the gate electrode provides an electric field across the dielectric layer, which dramatically increases the source-to-drain conductivity of the semiconductor layer. This change permits electrical conduction between the source and the drain electrodes. Typically, the gate electrode, the source electrode, and the drain electrode are fabricated by patterning. In general, the semiconductor layer is also patterned, in order to minimize stray conduction (i.e., cross-talk) between neighboring circuit elements.
Liquid crystal displays commonly employ amorphous silicon (xe2x80x9ca-Sixe2x80x9d), thin-film transistors (xe2x80x9cTFTxe2x80x9d) as switching devices for display pixels. These TFTs typically have a bottom-gate configuration. Within one pixel, a thin-film capacitor typically holds a charge transferred by the switching TFT. Thin-film transistors can be fabricated to provide high performance. Fabrication processes, however, can result in significant cost.
Referring to FIG. 1, a thin-film transistor, having typical contact structures, and a capacitor is illustrated in cross-section. The transistor and capacitor include bottom electrodes 153, 155 (bottom electrode 153 is the gate electrode for the transistor), a silicon nitride (xe2x80x9cSiNxe2x80x9d) dielectric layer 154, an a-Si layer 156, an n+ a-Si contact layer 158, drain and pixel electrodes 159, and capacitor top electrode 192. The a-Si layer 156, the n+ a-Si contact layer 158 and the electrodes 159 are all patterned layers.
The n+ a-Si contact layer 158 is typically 40 nm thick and provides an ohmic contact between the a-Si layer 156 and the electrodes 159. The patterning of the n+ a-Si layer 158 generally requires overetching to assure complete removal of the n+ a-Si contact layer 158 along the channel portion of the a-Si layer 156. Thus, a portion of the a-Si layer 156 is removed during this overetch step. Hence, the a-Si layer 156, as-deposited, is traditionally 160 nm or more in thickness.
The high cost of manufacturing thin-film transistors results in part from patterning steps, which typically require the use of expensive photolithography equipment and masks, coating steps and etching steps. An a-Si layer is typically patterned to leave islands of semiconductor material and thereby reduce leakage currents. Formation of the structures illustrated in FIG. 1 might require three lithography steps and four etching steps. Trends toward making higher performance devices make precision patterning even more important and manufacturing cost even greater.
Certain electronic devices, however, require low cost rather than high performance components. For such devices, it remains desirable to have means to obtain better yield and lower cost of manufacturing.
The invention is based in part on the realization that a low cost display device transistor array having a shared, lightly counter-doped semiconductor layer may support good image resolution while providing tolerable leakage currents. The invention features electronic circuits that have a lower manufacturing cost and methods of making electronic circuits that involve simpler processing steps. The circuits are particularly useful for addressing display media in a display device.
In a preferred embodiment, the circuits comprise thin-film transistors (xe2x80x9cTFTxe2x80x9d) that share a lightly counter-doped, continuous semiconductor layer that mediates current between source and drain of each transistor in an array of transistors (semiconductor layers that mediate current are herein also referred to as xe2x80x9cactive layersxe2x80x9d). The semiconductor layer may be unpatterned. The layer may be continuous in two dimensions, e.g., it may be shared by, and continuous between, TFTs in a two-dimensional array. The display medium controlled by the circuits may tolerate leakage currents that flow through the continuous semiconductor layer. Devices of the invention are of particular use in the fabrication of electrophoretic displays.
In a preferred embodiment, the continuous semiconductor layer is lightly counter-doped with boron dopant to increase its resistivity while still providing adequately functional TFTs (xe2x80x9cdopantxe2x80x9d herein refers to material intentionally added to a semiconductor, as opposed to xe2x80x9cimpuritiesxe2x80x9d, which herein refers to materials inherently present due to a manufacturing process). As-deposited a-Si typically is slightly n-type in its electrical characteristic. Addition of small amounts of a p-type dopant, such as boron, may neutralize a portion of the n-type character of the a-Si layer, and thereby increase its resistivity. The increased resistance may reduce leakage currents that pass via the a-Si layer. This reduction may permit smaller and more closely packed transistors, thus permitting improved display device resolution. The amount of added dopant may be chosen to provide a significant increase in resistance while still permitting the TFT to function, for example, by leaving an active layer with a reduced n-type or a slight p-type electrical characteristic.
Various embodiments of the invention provide numerous advantages over prior art TFTs and other thin-film devices. For example, TFT arrays may be fabricated with no patterning of a semiconductor layer, i.e. the active layer. This may eliminate a photolithographic step and a dry etching step. Hence, cost and throughput are improved. The invention may provide improved fabrication yield, due to simplified processing. Moreover, some embodiments may utilize a roll-to-roll substrate fabrication process. Continuous deposition of a semiconductor stack and metal 2 without a break in vacuum, for example, as well as an all-wet etching process, are compatible with roll-to-roll processing.
Though use of an unpatterned active layer may increase device leakage, appropriate selection of added dopant concentration and selection of the layout of a TFT array may provide acceptable performance. The spacing between transistors may be selected to obtain acceptable leakage currents. The geometry of the transistors may be selected to obtain an acceptable leakage current between a first data line and a second data line. Alternatively, the spacing between the first data line and a first pixel electrode may be chosen to provide an acceptable leakage current between the first data line and the first pixel electrode. Use of optimized doping in the active layer may permit closer packing of devices than otherwise possible.
Accordingly, in a first aspect, the invention features a thin-film transistor array that includes at least first and second transistors. Each of the first and second transistors include a shared silicon layer, extending continuously between the first and second transistors. The semiconductor layer is counter-doped to increase a resistivity of the semiconductor layer and reduce a leakage current through the semiconductor layer while permitting functioning of the transistor array. A source electrode is adjacent to the semiconductor layer (in many embodiments a contact layer is provided between the source and drain electrodes on the one hand and the same conductor layer on the other), a drain electrode is spaced from the source electrode and adjacent to the semiconductor layer, and a gate electrode is disposed adjacent to the dielectric layer.
The semiconductor layer may consist of silicon, which may be unpatterned. Hence, a silicon layer may be a continuous film of material, use of which may reduce the number of process steps involved in manufacturing the transistor array. The silicon layer may include amorphous silicon, and the dopant may be a p-type dopant, e.g., boron.
The first transistor may be a bottom gate or a top gate transistor. The first transistor may include a first pixel electrode of an electronic display, the first pixel electrode in communication with the source electrode of the first transistor, and the drain electrode of the first transistor is in communication with a first data line of the electronic display. A distance between the first pixel electrode and the first data line may be selected to provide an acceptable leakage current between the first pixel electrode and the first data line. Though use of an unpatterned silicon layer may lead to increased leakage current, transistor geometry may be adjusted to reduce leakage to tolerable levels.
Different geometrical aspects of a transistor array may be selected to reduce leakage. The distances between a pixel electrode and each of the adjacent data lines may be selected to provide an acceptable leakage current between the first data line and the second data line. At least one of the first data line, the second data line, the first transistor and the first pixel electrode may have a geometry selected to provide an acceptable leakage between the first data line and the second data line.
In a second aspect, the invention features an electronic display. The display includes a display medium, a first pixel electrode and a second pixel electrode provided adjacent to the display medium. A first thin-film transistor and a second thin-film transistor are in respective electrical communication with the first pixel electrode and the second pixel electrode.
The transistors include a shared continuous semiconductor layer that provides channels for the first thin-film transistor and the second thin-film transistor. The semiconductor layer is doped to increase a resistivity of the semiconductor layer and reduce a leakage current through the semiconductor layer while permitting functioning of the first and second thin-film transistors.
The electronic display may include any of a variety of display media, for example, an electrophoretic medium. An electrophoretic medium may have at least one type of particle and a suspending fluid, and may be encapsulated.
In a third aspect, the invention features a method of manufacturing an array of thin-film transistors. The method includes the steps of providing a substrate and forming adjacent to the substrate an unpatterned semiconductor layer. The semiconductor layer is doped to increase the resistivity of the semiconductor layer and reduce leakage currents through the semiconductor layer while permitting functioning of the transistor array.
The step of forming the unpatterned semiconductor layer may include forming an amorphous silicon film having p-type dopant. Forming an amorphous silicon film may include adding the p-type dopant to the amorphous silicon film, or co-depositing silicon and the p-type dopant.
A dielectric layer may be formed adjacent to the at least one gate electrode. Forming the dielectric layer, forming the unpatterned silicon layer and forming the metal layer which will, after patterning, form the source and drain electrodes may occur at during one visit of the substrate inside a single deposition chamber. Providing a substrate may include unwinding the substrate from a first roll and winding the substrate onto a second roll.
The method may further include providing a first pixel electrode of an electronic display in communication with the source electrode of the first transistor, and providing a first data line of the electronic display in communication with the drain electrode of the first transistor. The method may further include providing a second pixel electrode of an electronic display in communication with the source electrode of the second transistor and providing a second data line of the electronic display in communication with the drain electrode of the second transistor.
Various geometrical parameters may be adjusted to provide acceptable leakage currents. Geometrical parameters include the shapes of features and the spacings between features. Features include, for example, the data lines, the transistors and the pixel electrodes.
Forming may include mask steps consisting of a first mask step and a second mask step. At least one patterned gate electrode is formed in the first mask step, and at least one drain and one source electrode is formed in the second mask step. Hence some embodiments include exactly two mask steps. An additional mask step may be required to form contacts adjacent the edges of the display.